Magnetic Random Access Memory (MRAM) may be used to store information, coded in a binary representation as one or more bits, for later retrieval and use. While conventional memory techniques, such as flash memory, Static Random Access Memory (SRAM), and Dynamic Random Access Memory (DRAM), use a stored charge or flip-flops to store information, MRAM may use magnetization to indicate the presence of a stored “1” or a stored “0”. Two primary types of cell architecture may be used to implement MRAM, a resistor cross point array and a three-conductor memory cell array.
The simplest form of a resistor cross point memory array is a two conductor memory cell architecture shown in FIG. 1. In this architecture every MRAM cell is connected in parallel with every other MRAM cell in the array.
Referring to FIG. 1, a resistor cross point array includes an array of rows of metal conductors (x-direction) forming word lines 101 and columns of metal conductors (y-direction) forming bit lines 102. MRAM cells, or MRAM “bits,” 103 are located at each orthogonal crossing of the word lines and bit lines. The MRAM is typically composed of thousands or millions of MRAM cells. MRAM may also be divided into groups or blocks of MRAM cells.
Each MRAM cell 103 typically has at least five layers. These layers include first and second conductors, first and second magnetic layers, and a high-resistance thin-film barrier or dielectric located inbetween the first and second magnetic layer. The first conductor is a portion of bit line 102. The first magnetic layer 104 is electrically connected to the first conductor, and is typically made primarily of a nickel-iron alloy or a nickel-iron-cobalt alloy, may include a crystalline structure and possibly other components, other elements or compounds. The first magnetic layer may be a free ferromagnetic layer, referred to as the free, data or soft layer. The second conductor may be a portion of word line 101. Second magnetic layer 105 is electrically connected to the second conductor and may also have a nickel-iron primary composition, including a crystalline structure and other elements that may be different from the first magnetic layer. Second magnetic layer 105 may be a fixed layer, referred to as the fixed layer, the pinned layer, or the reference layer. Second magnetic layer 105 may have slightly different characteristics than first magnetic layer 104. The high-resistance thin-film barrier or dielectric 106 is positioned between the first and second magnetic layers.
The magnetization in the data layer may be set by an induced magnetic field resulting from electric currents through the respective conductors. The induced field may be varied, in magnitude and/or direction, by varying the magnitude or direction of the electric current passed through the respective conductors. The resulting magnetic field may be a function of the current passed through the word line (row conductors) creating a first magnetic field and the current passed through the bit line (column conductors) creating a second magnetic field. In order to store a value in the data layer, the vector sum of the two fields, resulting from an electrical current passing through the word line and the bit line, needs to be large enough to overcome the coercivity of the data layer so as to change the direction of the magnetization in the data layer. Additionally, the currents in the word line and the bit line must be small enough to ensure that the magnetic fields created do not affect the values stored in nearby MRAM cells. When MRAM cells are exposed to the induced magnetic field of either a bit line or a word line alone (as opposed to both a bit line and a word line) the condition is referred to as “half-select” as opposed to the selected MRAM bit receiving an induced magnetic field from both a selected bit line and a selected word line.
Writing to a memory cell in the cell architecture requires a relatively high magnetic field. To write information into an MRAM cell a current must be passed through both the word and bit lines of a selected memory cell. Current passing through bit line 102 creates a magnetic field around the bit line. Similarly, current passing through word line 107 creates a magnetic field around the word line. The magnetic field in the free layer, data layer, or soft layer may be established by coupling an induced magnetic field by passing an electric current through the respective conductors. The induced field may be varied, in magnitude and/or direction, by varying the magnitude or direction of the electric current passed through the respective conductors. In particular, the magnetization on each side of dielectric 106 effects the tunneling current (leakage current) that flows through the dielectric in the MRAM cell. Current in bit line 102 in the direction of arrow 108 and current in word line 107 in the direction of arrow 109 are additive to cause the magnetization in the free magnetic layer in MRAM cell 103. Current in the bit line induces a magnetic field in a direction referred to as the easy axis. Current in the word line induces a magnetic field in a direction referred to as the hard axis. When a read voltage is applied across the selected MRAM cell from the bit line to the word line a tunneling current flows across the barrier of the MRAM cell and the magnitude of this current is dependent on the relative direction of the magnetization between the free magnetic layer and the fixed magnetic layer.
When current is present in direction 108 in bit line 102 and direction 109 in word line 107 magnetic fields are induced in the data layer to cause a magnetization in the same direction of the magnetic field in the fixed layer then the magnetization's are parallel and the resistance of the memory cell is a first value. This configuration may be used to represent, for example, a stored “1.” Conversely, when direction 110 of the currents in bit line 102 and word line 101 induce magnetic fields in the data layer to cause a magnetization in the opposite direction of the magnetic field in the fixed layer the magnetization's are anti-parallel and the resistance of the memory cell is a second value somewhat greater than the first value. This configuration may be used to represent a stored “0.”
As described, the memory state is determined by the resistance state of the selected MRAM memory cell that is determined by the amount of current flowing between a selected word line and a selected bit line. For example, a state of parallel magnetizations will yield a higher current than an anti-parallel state. The higher level of current indicates the direction of magnetization in the free magnetic layer is in the same direction as the magnetization in the fixed magnetic layer (referred to as the parallel state) and that may represent a stored “1”, while a lower level of current may indicate an anti-parallel state with the direction of magnetization in the free magnetic layer is opposite to the direction of the magnetization in the fixed magnetic layer and that may represent a stored “0.” In a resistance cross point array isolation devices are not included to segregate memory cells from one another. This requires that sensing schemes include adjustments to compensate for the parallel nature of the memory cells. One type of sensing scheme is Equi-Potential-Isolation.
An MRAM cell array that includes a common read and write bit line conductor and a common read and write word line conductor is called a two-conductor MRAM cell array. In a two-conductor MRAM cell array, a set of write circuits are required for every group or “block” of memory cells. A block of memory cells may include, for example, one to two thousand rows and five hundred to four thousand columns. For each block, write current drivers are required at all four sides of the array. These current drivers occupy a large amount of area thus reduce the capacity of the MRAM memory device. With a two-conductor architecture an independent set of row write drivers is needed for every array block. In this configuration the difficulty in reading and writing data to and from an individual MRAM cell increases as the size of the array increases.
One type of three-conductor memory cell array includes a switching or “steering” device associated with each MRAM cell. In practice, this steering device, typically a transistor, is located in the silicon layer that is on the silicon substrate and under the memory layers. Although diodes have been suggested as steering devices, they have not been successfully demonstrated. The three-conductor memory cell array includes a low resistance bit line, a low resistance word line and a thin inter-cell conductor. In this configuration, each memory cell is connected to the low resistance bit line and the thin inter-cell conductor; the inter-cell conductor is also connected to a switch transistor located in the silicon substrate. Alternately, a metal word line or a low resistance word line may be electrically isolated from the cell but processed to physically pass sufficiently close to the memory cell to allow induced magnetic fields from the low resistance word line to control the data to be stored in the free magnetic layer of the MRAM cell. A second word line formed in the silicon substrate may be connected to the gate of the silicon switch transistor. When data is written into the memory cell, the silicon switch transistor is deselected (turned off by the second word line) and write currents are passed through the selected bit and word lines to cause magnetization of the free layer of the selected memory cell. When the memory cell is being read, no current is passed through the first metal word line while the second word line is asserted to select the silicon switch (turned on by the second word line) and a read potential is applied to the selected bit line. To retrieve data, a read current passes through the selected bit line, memory cell, inter-cell conductor, and the selected silicon switch transistor. A read sense amplifier connected to the selected bit line is then used to determine the resistance state of the memory cell from the resultant bit line current.
In a three-conductor memory cell array, the metal word line typically extends over the entire memory chip. By extending the metal word line over the entire memory chip only two write circuits are required, one located on the left side and one located on the right side of the chip, for the entire chip. This is in contrast to a two-conductor MRAM wherein write current drivers are required for each block of memory cells. By using the three-conductor memory cell array, fewer word line write drivers are required, so that more space is available for memory cells resulting in a larger capacity memory.
A second type of three-conductor MRAM cell includes a low resistance bit line, a low resistance word line and a thin sense line. In this configuration, the low resistance, metal bit line passes over, but may be electrically isolated from the thin sense line. The sense line is connected to one terminal of a memory cell and the other terminal of the memory cell is connected to the low resistance, metal word line. The sense line is connected to a small group of memory cells and to a switch transistor formed in the silicon substrate. The switch transistor is controlled by the metal bit line and is activated only during read operations. In this configuration, a write operation generates a current through the selected bit and word lines to set the magnetization direction of the free magnetic layer to correspond to the write data assigned to the selected memory cell. A read operation applies a read potential to the selected word line with the switch transistor turned on to pass a read current from the selected word line, through the selected memory cell, the thin sense line, the switch transistor and into a sense amplifier located in the substrate.
In the second type of a three-conductor memory cell array, the metal bit line conductor extends over the entire length of memory chip. By extending the conductor over the entire length of the memory chip only two write circuits are required, one on the top and one on the bottom of the chip, rather than requiring write circuits for each block of memory cells as in a two-conductor MRAM. Thus, by using the three-conductor memory cell array, more memory cells may be included on a chip resulting in more efficient use of the chip real estate.
The memory cells are not limited to any particular type of device. For example, the memory cells may be Spin Dependent Tunneling (“SDT”) devices. A typical SDT device includes a “fixed” magnetic layer and a “free” magnetic layer. The fixed layer has a magnetization that is oriented in a plane, but fixed so as to not rotate in the presence of an applied magnetic field on a range of interest. The free layer has a magnetization orientation that is not fixed. Rather, the magnetization may be oriented in either of two directions along an axis (the “easy” axis) lying in the plane. If the magnetization of the free and fixed layers are in the same direction, the orientation is said to be “parallel.” If the magnetization of the free and fixed layers are in opposite directions, the orientation is said to be “anti-parallel.” The free layer and the fixed layer are separated by an insulating tunnel barrier. The insulating tunnel barrier allows quantum mechanical tunneling to occur between the free and fixed layers. This tunneling phenomenon is electron spin dependent, making the resistance of the SDT device a function of the relative orientations of the magnetization of the free and fixed layers.
For instance, the resistance of the memory cell is a first value R if the orientation of magnetization of the free and fixed layers is parallel. Resistance of the memory cell is increased to a second value R+deltaR if the magnetization orientation is changed from parallel to anti-parallel. A typical resistance R may be about one megaohm. A typical change in resistance deltaR may be about 10% of the resistance of R.
FIG. 2 shows one three-conductor memory cell architecture in which sense conductor 201 is added to the two-conductor memory cell architecture. In this configuration word lines 101 and bit lines 102 are used to write data into a selected MRAM cell. Sense conductor 201 may be used to read data out from the MRAM cells. In this configuration the sense line is connected to one terminal of the MRAM memory cell and is typically formed as a very thin conducting layer. Here word lines 101 may be a thicker low resistance conductor, electrically insulated from the sense line, that runs in parallel to the sense line. A fairly high current may be applied to this word line 101 for writing.
With the second type of three-conductor cell architecture, the set of column write drivers is reduced to only one set located at the top and bottom of the memory chip (over many memory array blocks) eliminating column write drivers from between memory array blocks. Thus, the three-conductor cell architecture improves the area efficiency ratio by making the memory chip smaller, eliminating the inter-block column write drivers. In addition the column decode circuitry is placed underneath the three-conductor memory cell array to further reduce space requirements. However, the three-conductor memory cell does not reduce or alleviate the space requirements for developing currents in the row direction.